1. Field of the Invention
The present invention relates to JFETs, and especially JFETS designed to be suitable for use in helping to control NEMS/MEMS scale machines (herein called “NEMS/MEMS machines,” see also, “NEMS/MEMS scale” in the DEFINITIONS section). The present invention further relates to devices which include both the NEMS/MEMS machine and at least some of the circuitry for controlling the operation of the NEMS/MEMS machine (see definition section). These combinations of the NEMS/MEMS machine hardware set and at least a portion of its control circuitry (e.g. a JFET) will sometimes herein be referred to as “NEMS/MEMS devices.”
2. Description of the Related Art
As shown in FIG. 1, conventional SOI-NEMS/MEMS device (see definition of SOI in the DEFINITIONS section) 100, includes: An electronics chip consisting mostly of complementary metal oxide (“CMOS”) semiconductor transistors, but active electronic transistors in general, 102; bonded conduction path 112; and NEMS/MEMS chip 113. Electronics chip 102 includes: contact pad/s 104, 110; demodulator/filter/pre-amp/reference module 106; and amplifier 108. NEMS/MEMS chip 113 includes: mechanical springs and masses 114; fingers often used for electrostatic actuation 116; anchor 118; proof mass 119; and contact pads 120. Sub-assembly 114 (including proof mass 119) moves in the directions indicated by arrows D1 and D2: (i) to create an electrical signal; and/or (ii) in response to an electrical signal. This sort of conventional NEMS/MEMS device is part of many commercial products and/or proposed products, such as accelerometers, gyroscopes, electrical switches, resonators, timing devices, optical switches, optical gratings, and microfluidic devices. Many commercial NEMS/MEMS devices are made with thicker suspended parts to obtain higher mass and greater sense capacitances. This has been obtained through using SOI wafers and etching them using DRIE processing techniques. Even without SOI substrates, using processes such as SCREAM, high aspect ratio NEMS/MEMS devices are commercially available.
There are two main architectures for electrically connecting the NEMS/MEMS machine and its associated transistors (e.g., field effect transistors, or “FETs,” for sensing a motion characteristic (see DEFINITIONS section)). These two main architectures, for electrically connecting transistor and machine are as follows: (i) putting the machine and the transistors respectively on two different chip substrates and electrically connecting them by conduction paths that have “conductor bonding” (see DEFINITIONS section); and (ii) putting the machine and transistor on a common chip substrate so that the machine and transistor are electrically connected to each other using only non-bonded conduction path(s). Architecture (i) will sometimes be referred to herein as the “hybrid technique” (or “hybrid architecture”). Architecture (ii) will sometimes be herein referred to as “monolithic integration.” The hybrid technique, where the integrated circuit and NEMS and/or MEMS machine components are fabricated independently and typically wire bonded or flip-chip bonded together, is shown in FIG. 1.
Most commercial MEMS sensor solutions use the hybrid integration process for electrical interface and signal conditioning. The hybrid-technique is often justified as a way to reduce complexity of CMOS integration with NEMS/MEMS. Monolithic integration with a highly complex electronics technology such as multi-level interconnect state-of-art CMOS can be expensive for monolithic integration. This is because, the NEMS/MEMS components often take much larger amount of real-estate on chip compared to the transistors needed for the sensor signal conditioning. Hence, buying a separate few-transistor signal conditioning chip, and bonding to a separate low-complexity NEMS/MEMS chip is often cost-effective. Although the hybrid technique offers the advantage of independent optimization of the integrated circuit and NEMS fabrication process flows, it is conventionally recognized that the cost for assembly and packaging can be higher than the cost of monolithic integration. Previously, various research groups have monolithically integrated MOSFETs into NEMS/MEMS devices for signal transduction. The focus generally has been on monolithic integration with CMOS transistors, assuming that one could integrate the NEMS/MEMS process with conventional state-of-art ultra-miniature CMOS technology. Since the number of transistors needed to obtain effective signal conditioning, co-integration of transistors within the NEMS/MEMS fabrication flow could enable an optimal cost/performance of NEMS/MEMS. Recent work has focused on integrating the MOS structures within NEMS/MEMS, partly owing to the fact that the DC power consumption in MOS transistors can be low due to high Ion/Ioff ratio of devices and very low gate leakage currents. However, MOS devices suffer from higher input referred noise due to the noisy conduction of carriers along the oxide-silicon interface. It has been widely recognized that the flicker noise for MOS transistors is inferior to that of JFET or Junction Field Effect Transistors, also known as Junction Gate Field Effect Transistors.
A NEMS/MEMS device, including a NEMS/MEMS machine and an associated transistor in the form of a JFET, is disclosed in U.S. Pat. No. 7,205,173 (“Brunson”). In Brunson, the JFET portions of the NEMS/MEMS device are in the form of “wells,” which is to say that the doping that creates the constituent regions of the Brunson JFET is accomplished by diffusing dopants into the wafer thickness (that is, in a direction substantially normal to the major surface of the semiconductor layer through which the diffusion occurs. In 173 Brunson, the doped wells forming the Brunson JFET do not extend all the way across the thickness of their semiconductor layer (that is, the wells do not extend from one major surface of the semiconductor, all the way to the opposite major surface. Because of the geometry of the well structures in Brunson, the channel conductance is squeezed (and sometimes pinched off) by depleted zone(s) that expand in the thickness direction of the semiconductor layer to control conduction. In Brunson, NEMS/MEMS were integrated with the JFET transistors monolithically, but the link between transistors and the NEMS/MEMS was purely electrical. The output of the NEMS/MEMS, being capacitive output, was linked to the transistor gates.
The following published documents may also include helpful background information: (i) Oilier, E., Duraffourg, L., Colinet, E., Durand, C., Renaud, D., Royet, A., Renaux, P., Casset, F., Robert, P., “Lateral MOSFET Transistor With Movable Gate for NEMS Devices Compatible With “In-IC” Integration,” Nano/Micro Engineered and Molecular Systems, 2008, NEMS 2008, 3rd IEEE International Conference on, vol., no., pp. 764-769, 6-9 Jan. 2008, http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=arnumber=4484439&isnumber=4484266; (ii) U.S. Pat. No. 6,531,331 (“Bennett”); (iii) U.S. Pat. No. 7,615,788 (“Kornegay”); (iv) U.S. Pat. No. 8,012,785 (“Liang”); (v) U.S. Pat. No. 7,989,889 (“Kerr”); (vi) US Patent Publication No. 2011/0101475 (“Parpia”); (vii) US Patent Publication No. 2010/0263997 (“Hilgers”); (viii) US Patent Publication No. 2011/0068374 (“Tan”); (ix) U.S. Pat. No. 7,759,924 (Shekhawat); (x) U.S. Pat. No. 7,868,403 (“Ivanov”); (xi) U.S. Pat. No. 6,797,534 (“Tu”); (xii) US Patent Publication No. 2010/0171569 (“Ionescu”); (xiii) US Patent Publication No. 2010/0314668 (“Ollier”); (xiv) US Patent Publication No. 2011/0026742 (“Huang”); (xv) US Patent Publication No. 2011/0057288 (“Tan”); (xvi) U.S. Pat. No. 5,880,921 (“Tham”); and (xii) Grogg, D., Tsamados, D., Badila, N. D., Ionescu, A. M., “Integration of MOSFET Transistors in MEMS Resonators for Improved Output Detection,” Solid-State Sensors, Actuators and Microsystems Conference, 2007, TRANSDUCERS 2007, International. vol., no., pp. 1709-1712, 10-14 June 2007, http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4300481&isnumber=430005 (xviii) US Patent No. US 2011/0024812 A1 (“Weinstein et al”); (xix) US Patent No. US 2008/0001658 A1 (“Mojarradi et al”); (xx) US Patent No. US 2007/0008013 A1 (“Fijany et al”); (xxi) Akarvardar et al. (US application 2007-0008013 A1).
Description of the Related Art Section Disclaimer: To the extent that specific publications are discussed above in this Description of the Related Art Section, these discussions should not be taken as an admission that the discussed publications (for example, published patents) are prior art for patent law purposes. For example, some or all of the discussed publications may not be sufficiently early in time, may not reflect subject matter developed early enough in time and/or may not be sufficiently enabling so as to amount to prior art for patent law purposes. To the extent that specific publications are discussed above in this Description of the Related Art Section, they are all hereby incorporated by reference into this document in their respective entirety(ies).